To access the full text documents, please follow this link: http://hdl.handle.net/2117/22528

Logic synthesis for manufacturability considering regularity and lithography printability
Machado, Lucas; Dal Bem, Vinicius; Moll Echeto, Francisco de Borja; Gómez Fernández, Sergio; Ribas, Renato P.; Reis, André Inacio
Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
Integrated circuits
Lithography
Design for manufacture
Integrated circuit layout
Lithography
IC layout
Integrated circuit manufacturing
Lithography printability
Logic synthesis
technology remapping tool
Yield loss
Cost function
Integrated circuit modeling
Layout
Libraries
Lithography
Semiconductor device modeling
Superluminescent diodes
Lithography
Regularity
Technology mapping
Yield model
Circuits integrats
Litografia
Attribution-NonCommercial-NoDerivs 3.0 Spain
http://creativecommons.org/licenses/by-nc-nd/3.0/es/
info:eu-repo/semantics/publishedVersion
info:eu-repo/semantics/conferenceObject
IEEE Computer Society Publications
         

Show full item record

Related documents

Other documents of the same author

Marranghello, Felipe S.; Dal Bem, Vinicius; Reis, André I.; Ribas, Renato P.; Moll Echeto, Francisco de Borja
Cortadella Fortuny, Jordi; Petit Silvestre, Jordi; Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja
Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja
Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja
 

Coordination

 

Supporters