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Lithography aware regular cell design based on a predictive technology model
Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja
Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. HIPICS - Grupo de Circuitos y Sistemas Integrados de Altas Prestaciones
As semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated that layout regularity reduces the increasing impact of process variations on circuit performance and reliability. The purpose of this paper is to present the layout design of a regular cell based on 1-D elements which reduces lithography perturbations (ALARC). We depict several undesirable lithography effects and how these effects determine several layout parameters in order to achieve the required line-pattern resolution.
Àrees temàtiques de la UPC::Enginyeria electrònica
Metal oxide semiconductors, Complementary
Electronics
Integrated circuit layout
Electrònica
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