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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
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dc.contributor | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.contributor.author | Machado, Lucas |
dc.contributor.author | Dal Bem, Vinicius |
dc.contributor.author | Moll Echeto, Francisco de Borja |
dc.contributor.author | Gómez Fernández, Sergio |
dc.contributor.author | Ribas, Renato P. |
dc.contributor.author | Reis, André Inacio |
dc.date | 2013 |
dc.identifier.citation | Machado, L. [et al.]. Logic synthesis for manufacturability considering regularity and lithography printability. A: IEEE Computer Society Symposium on VLSI. "ISVLSI 2013: 2013 IEEE Computer Society Annual Symposium on VLSI: Natal, Brazil: August 5-7, 2013". Natal: IEEE Computer Society Publications, 2013, p. 230-235. |
dc.identifier.citation | 978-1-4799-1331-2 |
dc.identifier.citation | 10.1109/ISVLSI.2013.6654638 |
dc.identifier.uri | http://hdl.handle.net/2117/22528 |
dc.language.iso | eng |
dc.publisher | IEEE Computer Society Publications |
dc.relation | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6654638&isnumber=6654605 |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject | Integrated circuits |
dc.subject | Lithography |
dc.subject | Design for manufacture |
dc.subject | Integrated circuit layout |
dc.subject | Lithography |
dc.subject | IC layout |
dc.subject | Integrated circuit manufacturing |
dc.subject | Lithography printability |
dc.subject | Logic synthesis |
dc.subject | technology remapping tool |
dc.subject | Yield loss |
dc.subject | Cost function |
dc.subject | Integrated circuit modeling |
dc.subject | Layout |
dc.subject | Libraries |
dc.subject | Lithography |
dc.subject | Semiconductor device modeling |
dc.subject | Superluminescent diodes |
dc.subject | Lithography |
dc.subject | Regularity |
dc.subject | Technology mapping |
dc.subject | Yield model |
dc.subject | Circuits integrats |
dc.subject | Litografia |
dc.title | Logic synthesis for manufacturability considering regularity and lithography printability |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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