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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
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dc.contributor | Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat |
dc.contributor.author | Vatajelu, Elena Ioana |
dc.contributor.author | Rodríguez Montañés, Rosa |
dc.contributor.author | Di Carlo, Stefano |
dc.contributor.author | Renovell, Michel |
dc.contributor.author | Prinetto, Paolo |
dc.contributor.author | Figueras Pàmies, Joan |
dc.date | 2015 |
dc.identifier.citation | Vatajelu, E., Rodriguez, R., Stefano Di Carlo, Renovell, M., Paolo Prinetto, Figueras, J. Power-aware voltage tuning for STT-MRAM reliability. A: IEEE European Test Symposium. "20th IEEE European test symposium (ETS): proceedings 2015: May 25-29, Cluj-Napoca, Romania". Cluj-Napoca: Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 1-6. |
dc.identifier.citation | 978-1-4799-7603-4 |
dc.identifier.citation | 10.1109/ETS.2015.7138748 |
dc.identifier.uri | http://hdl.handle.net/2117/83193 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7138748 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica |
dc.subject | Magnetic memory (Computers) |
dc.subject | STT-MRAM |
dc.subject | process variability |
dc.subject | reliability |
dc.subject | endurance |
dc.subject | voltage tuning |
dc.subject | power-aware analysis |
dc.subject | Memòria magnètica (Ordinadors) |
dc.title | Power-aware voltage tuning for STT-MRAM reliability |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract |