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Title:
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Evaluating A+B=K conditions in constant time
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Author:
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Cortadella, Jordi; Llaberia Griñó, José M.
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Other authors:
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Universitat Politècnica de Catalunya. Departament de Ciències de la Computació; Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
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Abstract:
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The authors consider a type of condition that can be evaluated without requiring a complete ALU (arithmetic logic unit) operation. The circuit that is presented detects the condition A+B=K (n-bit numbers) in constant time, avoiding the carry propagation delay. This circuit can be used to detect a wide spectrum of conditions in branch instructions. It can improve the processor performance by advancing the evaluation of conditions and eliminating the pipeline delays produced by these operations. |
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Abstract:
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Peer Reviewed |
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Subject(s):
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-Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
-Logic circuits
-Logic design
-Integrated circuits -- Very large scale integration
-Computer arithmetic and logic units
-Circuits
-Adders
-Propagation delay
-Performance evaluation
-Arithmetic
-Concurrent computing
-Very large scale integration
-Costs
-Tin
-Circuits lògics
-Estructura lògica
-Circuits integrats a molt gran escala |
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Rights:
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Document type:
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Article - Published version
Conference Object |
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Published by:
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Institute of Electrical and Electronics Engineers (IEEE)
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Share:
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