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A single event transient hardening circuit design technique based on strengthening
Calomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio
Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
In a near future of high-density and low-power technologies, the study of soft errors will not only be relevant for memory systems and latches of logic circuits, but also for the combinational parts of logic circuits which seriously affect the system's operation. In this paper, we present a novel design strategy to reduce the impact of radiation-induced single event transients (SET) on logic circuits. This design style achieves SET mitigation by Strengthening the sensitive node using a likeness to feedback techniques. We have analyzed several techniques from hardening radiation at transistor level to a single event transient in 7nm FinFET devices. Simulation results have shown the proposed method has higher soft error robustness than the existing ones.
Peer Reviewed
Àrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència::Circuits de potència
Logic circuits
Computers--Circuits
Circuits lògics
Ordinadors--Circuits
info:eu-repo/semantics/publishedVersion
info:eu-repo/semantics/conferenceObject
Institute of Electrical and Electronics Engineers (IEEE)
         

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