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Error probability in synchronous digital circuits due to power supply noise
Martorell Cid, Ferran; Pons, M; Rubio Sola, Jose Antonio; Moll Echeto, Francisco de Borja
Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. HIPICS - Grupo de Circuitos y Sistemas Integrados de Altas Prestaciones
This paper presents a probabilistic approach to model the problem of power supply voltage fluctuations. Error probability calculations are shown for some 90-nm technology digital circuits. The analysis here considered gives the timing violation error probability as a new design quality factor in front of conventional techniques that assume the full perfection of the circuit. The evaluation of the error bound can be useful for new design paradigms where retry and self-recovering techniques are being applied to the design of high performance processors. The method here described allows to evaluate the performance of these techniques by means of calculating the expected error probability in terms of power supply distribution quality.
Àrees temàtiques de la UPC::Enginyeria electrònica
Metal oxide semiconductors, Complementary
Electronics
Integrated circuits--Very large scale integration
Electrònica
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