Sparse linear solver for transistor-level circuit simulation

Abstract

Sparse linear solvers play a crucial role in transistor-level circuit simulation, especially for large-scale post-layout circuit simulation when considering parasitic effects. Along with the fast development of semiconductor, integrated circuit sizes are continually expanding, causing sparse linear solvers to consume more time and memory resources. Furthermore, circuit matrices frequently exhibit high sparsity and non-uniform distributions of non-zero elements, compounding the challenge of achieving efficient acceleration. In this talk, I will introduce our recently developed high-performance open-source sparse direct solvers for circuit simulation on CPU, GPU, and distributed heterogeneous clusters, respectively. Several innovative algorithms will be presented, including strategies for harnessing machine learning techniques to address irregular sparsity distribution patterns in circuit matrices for enhanced computational speed, as well as methods that embrace synchronization-free concepts to design GPU and heterogeneous distributed cluster acceleration mechanisms, thereby harnessing the substantial parallel computing capabilities. Moreover, I will also introduce an iterative solver leveraging an efficient spectral graph sparsification algorithm to enable fast power grid simulation. Compared with conventional spectral graph sparsification algorithm, our method demonstrates high efficiency while maintain high accuracy.