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Title:
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A hierarchical mathematical model for automatic pipelining and allocation using elastic systems
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Author:
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Cortadella, Jordi; Petit Silvestre, Jordi
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Other authors:
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Universitat Politècnica de Catalunya. Departament de Ciències de la Computació; Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
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Abstract:
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The advent of FPGA-based accelerators has encouraged the use of high-level synthesis (HLS) for rapid prototyping and design space exploration. In this context, design optimization at behavioral level becomes a critical task for the delivery of high-quality solutions. Time elasticity opens a new avenue of optimizations that can be applied after HLS and before logic synthesis, proposing new sequential transformations that expand beyond classical retiming and enlarge the register-transfer level (RTL) exploration space. This paper proposes a mathematical model for RTL transformations that exploit elasticity to select the best implementation for each functional unit and add pipeline registers to increase performance. Two simple examples are used to validate the effectiveness and potential benefits of the model. |
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Abstract:
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Peer Reviewed |
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Subject(s):
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-Àrees temàtiques de la UPC::Informàtica::Informàtica teòrica
-Logic circuits
-Field programmable gate arrays
-Logic design
-Elasticity
-High level synthesis
-Logic synthesis
-Mathematical transformations
-Behavioral level
-Design optimization
-Design space exploration
-Functional units
-High-quality solutions
-Pipeline registers
-Potential benefits
-Register transfer level
-Hierarchical systems
-Circuits lògics
-Matrius de portes programables per l'usuari
-Estructura lògica |
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Rights:
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Document type:
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Article - Submitted version
Conference Object |
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Published by:
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Institute of Electrical and Electronics Engineers (IEEE)
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