Review on suitable eDRAM configurations for next nano-metric electronics era

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RECERCAT Home > Universitat Politècnica de Catalunya > Documents de recerca > View document

To access the full text documents, please follow this link: http://hdl.handle.net/2117/119979

dc.contributor	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor	Universitat Politècnica de Catalunya. Departament d'Enginyeria de Sistemes, Automàtica i Informàtica Industrial
dc.contributor	Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.contributor	Universitat Politècnica de Catalunya. VIRTUOS - Virtualisation and Operating Systems
dc.contributor	Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.contributor.author	Amat, Esteve
dc.contributor.author	Canal Corretger, Ramon
dc.contributor.author	Calomarde Palomino, Antonio
dc.contributor.author	Rubio Sola, Jose Antonio
dc.date	2018-03
dc.identifier.citation	Amat, E., Canal, R., Calomarde, A., Rubio, A. Review on suitable eDRAM configurations for next nano-metric electronics era. "International journal of the Society of Materials Engineering for Resources.The Society of Materials Engineering for Resources of Japan", Març 2018, vol. 23, núm. 1, p. 22-29.
dc.identifier.citation	1347-9725
dc.identifier.uri	http://hdl.handle.net/2117/119979
dc.language.iso	eng
dc.relation	info:eu-repo/grantAgreement/ES/TEC2016-75151-C3-2-R
dc.relation	info:eu-repo/grantAgreement/ES/1PE/TEC2013-45638-C3-2-R
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject	Logic circuits -- Reliability
dc.subject	eDRAM
dc.subject	FinFET
dc.subject	sub-VT
dc.subject	SEU
dc.subject	Circuits lògics -- Fiabilitat
dc.title	Review on suitable eDRAM configurations for next nano-metric electronics era
dc.type	info:eu-repo/semantics/submittedVersion
dc.type	info:eu-repo/semantics/article
dc.description.abstract	We summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform their memory cell counterparts, we explored different technological proposals and operational regimes where it can be located. The best memory cell performance is observed for the 3T1D-eDRAM cell when it is based on FinFET devices. Both device variability and SEU appear as key reliability issues for memory cells at sub-22nm technology node.
dc.description.abstract	Peer Reviewed

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