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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Parcerisa Bundó, Joan Manuel |
dc.contributor.author | Sahuquillo, Julio |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.author | Duato, José |
dc.date | 2005-02 |
dc.identifier.citation | Parcerisa, J.M., Sahuquillo, J., González, A., Duato, J. On-chip interconnects and instruction steering schemes for clustered microarchitectures. "IEEE transactions on parallel and distributed systems", Febrer 2005, vol. 16, núm. 2, p. 130-144. |
dc.identifier.citation | 1045-9219 |
dc.identifier.citation | 10.1109/TPDS.2005.23 |
dc.identifier.uri | http://hdl.handle.net/2117/100490 |
dc.language.iso | eng |
dc.relation | http://ieeexplore.ieee.org/document/1374854/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Multiprocessors |
dc.subject | Logic design |
dc.subject | Clustered microarchitecture |
dc.subject | Intercluster communication |
dc.subject | On-chip interconnects |
dc.subject | Instruction steering |
dc.subject | Complexity |
dc.subject | Multiprocessadors |
dc.subject | Estructura lògica |
dc.title | On-chip interconnects and instruction steering schemes for clustered microarchitectures |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/article |
dc.description.abstract | |
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