Replacing 6T SRAMs with 3T1D DRAMs in the L1 data cache to combat process variability

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Título:	Replacing 6T SRAMs with 3T1D DRAMs in the L1 data cache to combat process variability
Autor/a:	Liang, Xiaoyao; Canal Corretger, Ramon; Wei, Gu-Yeon
Otros autores:	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. VIRTUOS - Virtualisation and Operating Systems
Abstract:	With continued technology scaling, process variations will be especially detrimental to six-transistor static memory structures (6T SRAMs). A memory architecture using three-transistor, one-diode DRAM (3T1D) cells in the L1 data cache tolerates wide process variations with little performance degradation, making it a promising choice for on-chip cache structures for next-generation microprocessors.
Abstract:	Peer Reviewed
Materia(s):	-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors -Memory management (Computer science) -Microprocessors -Cache memory -Cache storage -DRAM chips -Microprocessor chips -SRAM chips -System-on-chip -Transistors -Gestió de memòria (Informàtica) -Microprocessadors -Memòria ràpida de treball (Informàtica)
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Tipo de documento:	Artículo - Versión publicada Artículo
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Jing, Naifeng; Shen, Yao; Lu, Yao; Ganapathy, Shrikanth; Mao, Zhigang; Guo, Minyi; Canal Corretger, Ramon; Liang, Xiaoyao

Amat, Esteve; Canal Corretger, Ramon; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio

Aymerich Capdevila, Nivard; Ganapathy, Shrikanth; Rubio Sola, Jose Antonio; Canal Corretger, Ramon; González Colás, Antonio María

Valero, Alejandro; Sahuquillo, Julio; Petit, Salvador; Lorente, Vicente; Canal Corretger, Ramon; López, Pedro; Duato, José

Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio

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