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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Yazdanpanah Ahmadabadi, Fahimeh |
dc.contributor.author | Jiménez González, Daniel |
dc.contributor.author | Álvarez Martínez, Carlos |
dc.contributor.author | Etsion, Yoav |
dc.contributor.author | Badia Sala, Rosa Maria |
dc.date | 2013 |
dc.identifier.citation | Yazdanpanah, F. [et al.]. Analysis of the Task Superscalar architecture hardware design. A: International Conference on Computational Science. "2013 International Conference on Computational Science (Procedia Computer Science, 2013, v.18, p. 339-348)". Barcelona: Springer, 2013, p. 339-348. |
dc.identifier.citation | 1877-0509 |
dc.identifier.citation | 10.1016/j.procs.2013.05.197 |
dc.identifier.uri | http://hdl.handle.net/2117/23229 |
dc.language.iso | eng |
dc.publisher | Springer |
dc.relation | http://www.sciencedirect.com/science/article/pii/S1877050913003402 |
dc.relation | info:eu-repo/grantAgreement/ES/5PN/TIN2007-60625 |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/249013/EU/Exploiting dataflow parallelism in Teradevice Computing/TERAFLUX |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Hardware |
dc.subject | VHDL (Computer hardware description language) |
dc.subject | Task Superscalar |
dc.subject | Hardware task scheduler |
dc.subject | VHDL |
dc.subject | VHDL (Llenguatge de descripció de maquinari) |
dc.title | Analysis of the Task Superscalar architecture hardware design |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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