SORS: New DRAM architectures and FPGA-based frameworks to enable fundamentally better computing systems

Abstract

DRAM-based main memory is a critical component in modern computing systems. Data movement from the DRAM to the CPU incurs long latency and consumes a significant amount of energy. These costs are often exacerbated by the fact that much of the data brought into the caches is not reused by the CPU or accelerators, providing little benefit in return for the high latency and energy cost, partly due to the coarsegrained nature of DRAM data transfers and DRAM row activation. In the first part of this talk, we will describe a new, high-throughput, energy-efficient, and low-cost DRAM architecture, Sectored DRAM, that mitigates the excessive energy consumption of coarse-grained DRAM data transfers and row activation. Compared to a system with coarse-grained DRAM, Sectored DRAM reduces the DRAM energy consumption while improving performance, enabling significant system-wide energy savings. In the second part of the talk, we will introduce two new FPGA-based frameworks, PiDRAM and EasyDRAM. They can be used to develop real system prototypes with commodity DRAM chips, and showcase real, accurate system performance benefits for ideas that aim to tackle the data movement bottleneck. For example, Processing-in/Near- Memory (PiM/PnM), retention-aware intelligent refresh, and DRAM access latency reduction. Using EasyDRAM, we show that in-DRAM bulk data copy operations in real DRAM chips can improve system performance for copy-heavy workloads by 15X. We also describe the MetaSys framework that enables rapid implementation and evaluation of diverse hardware-software cooperative techniques in real hardware. Finally, we will describe the DRAM Bender infrastructure that enabled many discoveries into the robustness characteristics and the computation capability of real DRAM chips. We describe our ongoing work in BSC adapting DRAM Bender to provide support for testing DRAM chips in BSC’s MEEP cluster as part of the Severo Ochoa Mobility Program. We show preliminary data on high bandwidth memory reliability characteristics gathered using this infrastructure at BSC.