Turquoise - 12nm 32-core RISC-V chip with a coherent mesh fabric for datacenter applications

dc.contributor.author
Tan, Zhangxi
dc.date.accessioned
2026-01-29T01:14:40Z
dc.date.available
2026-01-29T01:14:40Z
dc.date.issued
2024-04-10
dc.identifier
Tan, Z. Turquoise - 12nm 32-core RISC-V chip with a coherent mesh fabric for datacenter applications. A: Severo Ochoa Research Seminars at BSC. «9th Severo Ochoa Research Seminar Lectures at BSC, Barcelona, 2023-24». Barcelona: Barcelona Super Computer Center. Education & Training team, 2024, p. 80-81.
dc.identifier
https://hdl.handle.net/2117/451832
dc.identifier.uri
http://hdl.handle.net/2117/451832
dc.description.abstract
In this talk, we will present Turquoise, a 64-bit 32-core Out-Of-Order RISC-V CPU chip with three levels of caches designed for datacenter applications supporting the RVA23 profile. Turquoise is fabbed with the TSMC 12nm process technology with a frequency of 2.0 GHz without overdrive. The die size is ~400 mm^2. The custom designed RISC-V core has a 512-bit vector engine supporting the full RISC-V vector extension 1.0. The core also has the latest RISC-V advance interrupt standard (AIA) and H-mode implementation to run the Xen virtualization software. Turquoise will be available with a server system board design in the E-ATX form factor. We will share our experience in architecture and silicon implementations along with our future designs of RISC-V chips.
dc.format
2 p.
dc.format
application/pdf
dc.language
eng
dc.publisher
Barcelona Super Computer Center. Education & Training team
dc.rights
http://creativecommons.org/licenses/by-nc-nd/4.0/
dc.rights
Open Access
dc.rights
Attribution-NonCommercial-NoDerivatives 4.0 International
dc.subject
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject
High performance computing
dc.subject
Càlcul intensiu (Informàtica)
dc.title
Turquoise - 12nm 32-core RISC-V chip with a coherent mesh fabric for datacenter applications
dc.type
Conference report


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