Bipolar transistor vertical vertical scaling framework

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dc.contributor	Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.contributor	Universitat Politècnica de Catalunya. MNT - Grup de Recerca en Micro i Nanotecnologies
dc.contributor.author	Castañer Muñoz, Luis María
dc.contributor.author	Alcubilla González, Ramón
dc.contributor.author	Benavent, A
dc.date	1994-12
dc.identifier.citation	Castañer, L.; Alcubilla, R.; Benavent, A. Bipolar transistor vertical vertical scaling framework. "Solid-state electronics", Desembre 1994, vol. 38, núm. 7, p. 1367-1371.
dc.identifier.citation	0038-1101
dc.identifier.citation	10.1016/0038-1101(94)00254-D
dc.identifier.uri	http://hdl.handle.net/2117/131231
dc.language.iso	eng
dc.relation	https://www.sciencedirect.com/science/article/pii/003811019400254D
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::Transistors
dc.subject	Transistors
dc.subject	Transistors
dc.title	Bipolar transistor vertical vertical scaling framework
dc.type	info:eu-repo/semantics/publishedVersion
dc.type	info:eu-repo/semantics/article
dc.description.abstract	Scaling factors for current and transit time are derived for polysilicon emitter, silicon based heterojunction bipolar transistors. It is shown that a simple set of analytical equations in integral form can be used to analyse the above scaling properties and by introducing two “heterojunction factors” can be extended to the scaling analysis of heterojunction bipolar transistors.
dc.description.abstract	Peer Reviewed

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