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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Jha, Sudhanshu Shekhar |
dc.contributor.author | Heirman, Wim |
dc.contributor.author | Falcón Samper, Ayose Jesús |
dc.contributor.author | Tubella Murgadas, Jordi |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.author | Eeckhout, Lieven |
dc.date | 2016 |
dc.identifier.citation | Jha, S., Heirman, W., Falcón, A., Tubella, J., González, A., Eeckhout, Lieven. Shared resource aware scheduling on power-constrained tiled many-core processors. A: ACM International Conference on Computing Frontiers. "CF'16: Proceedings of 2016 ACM International Conference on Computing Frontiers". Como: Association for Computing Machinery (ACM), 2016, p. 365-368. |
dc.identifier.citation | 978-1-4503-4128-8 |
dc.identifier.citation | 10.1145/2903150.2903490 |
dc.identifier.uri | http://hdl.handle.net/2117/100850 |
dc.language.iso | eng |
dc.publisher | Association for Computing Machinery (ACM) |
dc.relation | http://dl.acm.org/citation.cfm?id=2903490 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Microprocessors -- Energy consumption |
dc.subject | Dynamic cores |
dc.subject | Frequency adaptation |
dc.subject | Last-level caches |
dc.subject | Many core |
dc.subject | Many-core processors |
dc.subject | Power management algorithms |
dc.subject | Shared resources |
dc.subject | Thread migration |
dc.subject | Microprocessadors -- Consum d'energia |
dc.title | Shared resource aware scheduling on power-constrained tiled many-core processors |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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