To access the full text documents, please follow this link: http://hdl.handle.net/2117/122769
dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Benedicte Illescas, Pedro |
dc.contributor.author | Hernandez, C. |
dc.contributor.author | Abella Ferrer, Jaume |
dc.contributor.author | Cazorla Almeida, Francisco Javier |
dc.date | 2018 |
dc.identifier.citation | Benedicte, P., Hernandez, C., Abella, J., Cazorla, F. J. HWP: hardware support to reconcile cache energy, complexity, performance and WCET estimates in multicore real-time systems. A: Euromicro Conference on Real-Time Systems. "29th International Conference on Probabilistic, Combinatorial and Asymptotic Methods for the Analysis of Algorithms (AofA 2018): June 25-29, 2018, Uppsala, Sweden". Wadern: Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2018. |
dc.identifier.citation | 978-3-95977-078-1 |
dc.identifier.citation | 10.4230/LIPIcs.ECRTS.2018.3 |
dc.identifier.uri | http://hdl.handle.net/2117/122769 |
dc.language.iso | eng |
dc.publisher | Schloss Dagstuhl - Leibniz-Zentrum für Informatik |
dc.relation | http://drops.dagstuhl.de/opus/volltexte/2018/9000/ |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles |
dc.subject | High performance computing |
dc.subject | Multicores |
dc.subject | Multilevel caches |
dc.subject | Real-time systems |
dc.subject | WCET |
dc.subject | Complex networks |
dc.subject | Embedded systems |
dc.subject | Hardware |
dc.subject | Integrated circuit design |
dc.subject | Interactive computer systems |
dc.subject | Interconnection networks (circuit switching) |
dc.subject | Reliability |
dc.subject | Cache coherence protocols |
dc.subject | Guaranteed performance |
dc.subject | Hardware mechanism |
dc.subject | High performance processors |
dc.subject | Multi-cores |
dc.subject | Multi-level cache |
dc.subject | Reduced coherences |
dc.subject | WCET |
dc.subject | Real time systems |
dc.subject | Càlcul intensiu (Informàtica) |
dc.title | HWP: hardware support to reconcile cache energy, complexity, performance and WCET estimates in multicore real-time systems |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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