Title:
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Self-adaptive hardware architecture with parallel processing capabilities and dynamic reconfiguration
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Author:
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Soto Vargas, Javier; Moreno Aróstegui, Juan Manuel; Madrenas Boadas, Jordi; Cabestany Moncusí, Joan
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Other authors:
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Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. ISSET - Integrated Smart Sensors and Health Technologies |
Abstract:
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This paper describes a new self-adaptive hardware architecture
with fault tolerance capabilities and a development
system that allows the creation of applications. This bioinspired
architecture is based on an array of cells with capacity for
parallel processing, which implements in a distributed way
self-adaptive capabilities, like self-routing, self-placement
and runtime self-configuration. This cell array together with
a component-level routing constitutes a SANE (Self-Adaptive
Networked Entity). An integrated development environment
and a physical prototype based on two FPGA boards has
been built in order to assess the features of the proposed
architecture. |
Abstract:
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Peer Reviewed |
Subject(s):
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-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles -Parallel programming (Computer science) -Self-adaptation -Self-configuration -Self-routing -Self-placement -Multicomputer -MIMD -Fault tolerance -Dynamic reconfiguration -Programació en paral·lel (Informàtica) |
Rights:
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Document type:
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Article - Published version Conference Object |
Published by:
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Association for Computing Machinery (ACM)
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