Title:
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A self-adaptive hardware architecture with fault tolerance capabilities
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Author:
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Soto, Javier; Moreno Aróstegui, Juan Manuel; Cabestany Moncusí, Joan
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Other authors:
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Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. AHA - Arquitectures Hardware Avançades |
Abstract:
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This paper describes a Fault Tolerance System (FTS) implemented in a new self-adaptive hardware architecture. This architecture is based on an array of cells that implements in a distributed way self-adaptive capabilities. The cell includes a configurable multiprocessor, so it can have between one and four processors working in parallel, with a programmable configuration mode that allows selecting the size of program and data memories. The self-elimination and self-replication capabilities of cell(s) are performed when the FTS detects a failure in any of the processors that include it, so that this cell(s) will be self-discarded for future implementations. Other adaptive capabilities of the system are self-routing, self-placement and runtime self-configuration. Additionally, it is described as an example application and a software tool that has been implemented to facilitate the development of applications to test the system. |
Abstract:
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Peer Reviewed |
Subject(s):
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-Àrees temàtiques de la UPC::Informàtica::Hardware -Computer architecture -Dynamic fault tolerance -MIMD -Self-adaptive -Self-placement -Self-replication -Self-routing -Arquitectura d'ordinadors |
Rights:
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Attribution-NonCommercial-NoDerivs 3.0 Spain
http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
Document type:
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Article - Published version Article |
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