A systolic algorithm for the fast computation of the connected components of a graph

Inicio | ¿Qué es? | Contacto

English | Català

Consultar RECERCAT

Por comunidades y
colecciones Por fecha Por autores Por títulos Por temas (CDU)

Consultar departamento

Por fecha Por autores Por títulos Por temas (CDU)

Estadisticas

Del documento Todo RECERCAT

Mi RECERCAT

Entrar Alertas por correo-e

Directorio de otros repositorios

RECERCAT Principal > Universitat Politècnica de Catalunya > Documents de recerca > Visualizar documento

Para acceder a los documentos con el texto completo, por favor, siga el siguiente enlace: http://hdl.handle.net/2117/106368

dc.contributor	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor	Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.contributor.author	Núñez, Fernando J.
dc.contributor.author	Valero Cortés, Mateo
dc.date	1988
dc.identifier.citation	Núñez, F., Valero, M. A systolic algorithm for the fast computation of the connected components of a graph. A: IEEE International Symposium on Circuits and Systems. "1988 IEEE International Symposium on Circuits and Systems: Espo, Finland, 7-9 June 1988". Espoo: Institute of Electrical and Electronics Engineers (IEEE), 1988, p. 2267-2270.
dc.identifier.citation	10.1109/ISCAS.1988.15396
dc.identifier.uri	http://hdl.handle.net/2117/106368
dc.language.iso	eng
dc.publisher	Institute of Electrical and Electronics Engineers (IEEE)
dc.relation	http://ieeexplore.ieee.org/document/15396/
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject	Parallel algorithms
dc.subject	Multiprocessors
dc.subject	Cellular arrays
dc.subject	Computer architecture
dc.subject	Multiprocessing systems
dc.subject	Algorismes paral·lels
dc.subject	Multiprocessadors
dc.title	A systolic algorithm for the fast computation of the connected components of a graph
dc.type	info:eu-repo/semantics/publishedVersion
dc.type	info:eu-repo/semantics/conferenceObject
dc.description.abstract	The authors consider the description of a systolic algorithm to solve the connected-component problem. It is executed in a ring topology with N processors, requiring O(Nlog N) time without regard to the graph's sparsity. The algorithm-partitioning issue is also addressed, indicating how to optimally map the computations into fixed-size rings or linear arrays. The proposed algorithm leads to simple processing elements, data addressing, and control. These points make the systolic array highly implementable.
dc.description.abstract	Peer Reviewed

Mostrar el registro sencillo del ítem

Documentos relacionados

Otros documentos del mismo autor/a

A block algorithm for the algebraic path problem and its execution on a systolic array

Núñez, Fernando J.; Valero Cortés, Mateo

Dynamic-vector execution on a general purpose EDGE chip multiprocessor

Duric, Milovan; Palomar Pérez, Óscar; Smith, Aaron; Stanic, Milan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo; Burger, Doug; Veidenbaum, Alexander V

AMMC: advance multi-core memory controller

Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo

Graph partitioning applied to DAG scheduling to reduce NUMA effects

Sánchez Barrera, Isaac; Casas, Marc; Moreto Planas, Miquel; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo

Vector processing-aware advanced clock-gating techniques for low-power fused multiply-add

Ratkovic, Ivan; Palomar Pérez, Óscar; Stanic, Milan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo

Accesibilidad | Aviso legal | Política de Cookies | Documentos de uso interno

Coordinación

Patrocinio