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Dynamic-vector execution on a general purpose EDGE chip multiprocessor
Duric, Milovan; Palomar Pérez, Óscar; Smith, Aaron; Stanic, Milan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo; Burger, Doug; Veidenbaum, Alexander V
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d´Altes Prestacions
This paper proposes a cost-effective technique that morphs the available cores of a low power chip multiprocessor (CMP) into an accelerator for data parallel (DLP) workloads. Instead of adding a special-purpose vector architecture as an accelerator, our technique leverages the resources of each CMP core to mimic the functionality of a vector processor. The morphing provides dynamic vector execution (DVX) on a general purpose CMP, by adding minimal hardware for vector control. DVX enhances the vector execution by dynamically configuring the allocation of compute and memory resources to match particular workload requirements. As an energy efficient substrate, we utilize modest dual issue cores based on an Explicit Data Graph Execution (EDGE) architecture. The results show that a DVX enabled 4-core EDGE CMP improves the energy-delay product over 14x, at the cost of only 1.1% of additional area. We compare DVX against a CMP that adds a dedicated DLP accelerator based on a conventional high performance vector design. The vector accelerator increases the area footprint over 74%, which greatly affects the cost of the modest processor. DVX avoids the additional costs and yet gains over 86% of the speedup obtained with the dedicated accelerator.
This work has been partially funded by the Spanish Government (TIN2012-34557), the European Research Council under the European Unions 7th FP (FP/2007-2013) / ERC GA n. 321253. and Microsoft Research
Peer Reviewed
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
Microprocessors
Computer architecture
DLP accelerator
DVX enabled 4-core EDGE CMP
EDGE architecture
Cost-effective technique
Data parallel workloads
Dedicated accelerator
Dynamic vector execution
Energy efficient substrate
Energy-delay product
Explicit data graph execution
Functionality
General purpose CMP
General purpose EDGE chip
Multiprocessor
High performance vector design
Low power chip multiprocessor
Minimal hardware
Modest processor
Special-purpose vector architecture
Vector accelerator
Vector control
Vector processor
Microprocessor chips
Multiprocessing systems
Computational modeling
Computer architecture
Hardware
Instruction sets
Message systems
Registers
Vectors
Microprocessadors
Arquitectura d'ordinadors
Attribution-NonCommercial-NoDerivs 3.0 Spain
http://creativecommons.org/licenses/by-nc-nd/3.0/es/
info:eu-repo/semantics/publishedVersion
info:eu-repo/semantics/conferenceObject
Institute of Electrical and Electronics Engineers (IEEE)
         

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