Para acceder a los documentos con el texto completo, por favor, siga el siguiente enlace: http://hdl.handle.net/2117/27788
dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
---|---|
dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Duric, Milovan |
dc.contributor.author | Palomar Pérez, Óscar |
dc.contributor.author | Smith, Aaron |
dc.contributor.author | Stanic, Milan |
dc.contributor.author | Unsal, Osman Sabri |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.author | Burger, Doug |
dc.contributor.author | Veidenbaum, Alexander V |
dc.date | 2014 |
dc.identifier.citation | Duric, M. [et al.]. Dynamic-vector execution on a general purpose EDGE chip multiprocessor. A: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. "International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XIV): proceedings: July 14-17, 2014: Samos, Greece". Samos: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 18-25. |
dc.identifier.citation | 978-1-4799-3770-7 |
dc.identifier.citation | 10.1109/SAMOS.2014.6893190 |
dc.identifier.uri | http://hdl.handle.net/2117/27788 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6893190 |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Microprocessors |
dc.subject | Computer architecture |
dc.subject | DLP accelerator |
dc.subject | DVX enabled 4-core EDGE CMP |
dc.subject | EDGE architecture |
dc.subject | Cost-effective technique |
dc.subject | Data parallel workloads |
dc.subject | Dedicated accelerator |
dc.subject | Dynamic vector execution |
dc.subject | Energy efficient substrate |
dc.subject | Energy-delay product |
dc.subject | Explicit data graph execution |
dc.subject | Functionality |
dc.subject | General purpose CMP |
dc.subject | General purpose EDGE chip |
dc.subject | Multiprocessor |
dc.subject | High performance vector design |
dc.subject | Low power chip multiprocessor |
dc.subject | Minimal hardware |
dc.subject | Modest processor |
dc.subject | Special-purpose vector architecture |
dc.subject | Vector accelerator |
dc.subject | Vector control |
dc.subject | Vector processor |
dc.subject | Microprocessor chips |
dc.subject | Multiprocessing systems |
dc.subject | Computational modeling |
dc.subject | Computer architecture |
dc.subject | Hardware |
dc.subject | Instruction sets |
dc.subject | Message systems |
dc.subject | Registers |
dc.subject | Vectors |
dc.subject | Microprocessadors |
dc.subject | Arquitectura d'ordinadors |
dc.title | Dynamic-vector execution on a general purpose EDGE chip multiprocessor |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
dc.description.abstract | |
dc.description.abstract |