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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Gibert Codina, Enric |
dc.contributor.author | Sánchez, Jesús |
dc.contributor.author | González Colás, Antonio María |
dc.date | 2003 |
dc.identifier.citation | Gibert, E., Sánchez, J., González, A. Local scheduling techniques for memory coherence in a clustered VLIW processor with a distributed data cache. A: International Symposium on Code Generation and Optimization. "International Symposium on Code Generation and Optimization, CGO 2003: 23-26 March 2003, San Francisco, California". San Francisco, CA: Institute of Electrical and Electronics Engineers (IEEE), 2003, p. 193-203. |
dc.identifier.citation | 0-7695-1913-X |
dc.identifier.citation | 10.1109/CGO.2003.1191545 |
dc.identifier.uri | http://hdl.handle.net/2117/100451 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/1191545/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Cache memory |
dc.subject | Interleaved storage |
dc.subject | Processor scheduling |
dc.subject | Synchronisation |
dc.subject | Parallel architectures |
dc.subject | Cache storage |
dc.subject | Parallel memories |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.subject | Memòria ràpida de treball (Informàtica) |
dc.title | Local scheduling techniques for memory coherence in a clustered VLIW processor with a distributed data cache |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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