Software prefetching for software pipelined loops

All of RECERCAT

To access the full text documents, please follow this link: http://hdl.handle.net/2117/105151

Title:	Software prefetching for software pipelined loops
Author:	Sánchez, Jesús; González Colás, Antonio María
Other authors:	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
Abstract:	The paper investigates the interaction between software pipelining and different software prefetching techniques for VLIW machines. It is shown that processor stalls due to memory dependencies have a great impact into execution time. A novel heuristic is proposed and it is show to outperform previous proposals.
Abstract:	Peer Reviewed
Subject(s):	-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors -Software architecture -Prefetching -Delay -Processor scheduling -Pipeline processing -Registers -VLIW -Proposals -Degradation -Argon -Programari -- Disseny
Rights:
Document type:	Article - Published version Conference Object
Published by:	Institute of Electrical and Electronics Engineers (IEEE)
Share: