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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Jha, Sudhanshu Shekhar |
dc.contributor.author | Heirman, Wim |
dc.contributor.author | Falcón Samper, Ayose Jesus |
dc.contributor.author | Tubella Murgadas, Jordi |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.author | Eeckhout, Lieven |
dc.date | 2017-02-01 |
dc.identifier.citation | Jha, S., Heirman, W., Falcon, A., Tubella, J., González, A., Eeckhout, Lieven. Shared resource aware scheduling on power-constrained tiled many-core processors. "Journal of parallel and distributed computing", 1 Febrer 2017, vol. 100, p. 30-41. |
dc.identifier.citation | 0743-7315 |
dc.identifier.citation | 10.1016/j.jpdc.2016.10.001 |
dc.identifier.uri | http://hdl.handle.net/2117/97578 |
dc.language.iso | eng |
dc.relation | http://www.sciencedirect.com/science/article/pii/S0743731516301186 |
dc.rights | Attribution 3.0 Spain |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Microprocessors -- Energy consumption |
dc.subject | Many-core tiled architecture |
dc.subject | Thread migration |
dc.subject | Power budget |
dc.subject | Adaptive microarchitecture |
dc.subject | Microprocessadors -- Consum d'energia |
dc.title | Shared resource aware scheduling on power-constrained tiled many-core processors |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/article |
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