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dc.contributor | Universitat Politècnica de Catalunya. Departament de Llenguatges i Sistemes Informàtics |
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dc.contributor | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
dc.contributor.author | Cortadella, Jordi |
dc.contributor.author | San Pedro Martín, Javier de |
dc.contributor.author | Nikitin, Nikita |
dc.contributor.author | Petit Silvestre, Jordi |
dc.date | 2013 |
dc.identifier.citation | Cortadella, J. [et al.]. Physical-aware system-level design for tiled hierarchical chip multiprocessors. A: International Symposium on Physical Design. "ISPD '13: Proceedings of the 2013 ACM International Symposium on Physical Design: March 24-27, 2013, Stateline, Nevada". Stateline, Nevada: ACM Press. Association for Computing Machinery, 2013, p. 3-10. |
dc.identifier.citation | 978-1-4503-1867-9 |
dc.identifier.citation | 10.1145/2451916.2451920 |
dc.identifier.uri | http://hdl.handle.net/2117/20573 |
dc.language.iso | eng |
dc.publisher | ACM Press. Association for Computing Machinery |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Multiprocessors |
dc.subject | Network-on-chip |
dc.subject | Floorplanning |
dc.subject | Wire planning |
dc.subject | Chip multiprocessor |
dc.subject | Multiprocessadors |
dc.title | Physical-aware system-level design for tiled hierarchical chip multiprocessors |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract |