dc.contributor.author
Bafleur, Marise
dc.contributor.author
Buxo, Juan
dc.contributor.author
Puig i Vidal, Manuel
dc.contributor.author
Givelin, P.
dc.contributor.author
Macary, V.
dc.contributor.author
Sarrabayrouse, G.
dc.date.issued
2009-06-19T08:21:42Z
dc.date.issued
2009-06-19T08:21:42Z
dc.identifier
https://hdl.handle.net/2445/8761
dc.description.abstract
The aim of this brief is to present an original design methodology that permits implementing latch-up-free smart power circuits on a very simple, cost-effective technology. The basic concept used for this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up.
dc.format
application/pdf
dc.format
application/pdf
dc.relation
Reproducció del document publicat a http://dx.doi.org/10.1109/16.216442
dc.relation
IEEE Transactions on Electron Devices, 1993, vol. 40, núm. 7, p. 1340-1342.
dc.relation
http://dx.doi.org/10.1109/16.216442
dc.rights
info:eu-repo/semantics/openAccess
dc.source
Articles publicats en revistes (Enginyeria Electrònica i Biomèdica)
dc.subject
Circuits integrats
dc.subject
Circuits electrònics
dc.subject
MOS integrated circuits
dc.subject
Power integrated circuits
dc.subject
Switching circuits
dc.title
Application of a floating well concept to a latch-up-free, low-cost, smart power high-side switch technology
dc.type
info:eu-repo/semantics/article
dc.type
info:eu-repo/semantics/publishedVersion
