FetchFlare: An open-source strided data prefetcher for high-performance cache hierarchies

Abstract

In recent years, the rise of open-source hardware has transformed the landscape of technology development. In particular, RISC-V has offered hardware designers the possibility of designing processors in a much cheaper way by leveraging a rich ecosystem of open-source designs that can be easily reused, extended, and customized. Although the RISC-V ecosystem is rapidly growing and open-source processors are becoming increasingly sophisticated, some advanced architectural techniques typically employed in commercial high-performance processors are still not prevalent in RISC-V open-source architectures. Among them, hardware prefetchers have been ubiquitous in highend processors for many years, but they are not as commonly found in open-source RISC-V processors. To bridge this gap, this work presents FetchFlare, a stride prefetcher for highperformance cache hierarchies. FetchFlare is able to capture the memory access patterns of applications, predict future memory accesses, and issue prefetch requests for them. We provide an open-source RTL implementation of FetchFlare and integrate it into a complete open-source setup formed by the OpenPiton framework, the Sargantana core, and the High-Performance Data Cache (HPDCache). Compared to a baseline system without prefetching, FetchFlare achieves an average speedup of 63%, avoids cache misses in the L1D and the L2 caches, and presents an average accuracy, coverage, and timeliness of 86%,39%, and 99%, respectively.

This work has been partially supported by the European HiPEAC Network of Excellence, by the Generalitat de Catalunya (contract 2021-SGR-00763), and by Lenovo-BSC Contract-Framework Contract (2022). The BZL project is funded by the Ministerio de Transformación Digital y de la Función Pública by the Plan de Recuperación, Transformación y Resiliencia - financed by the European Union - NextGenerationEU. This work is part of the project PID2023-146511NB-I00 funded by the Spanish Ministry of Science, Innovation and Universities MCIU/AEI/10.13039/501100011033 and EU ERDF.

Peer Reviewed

Postprint (author's final draft)