Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
Barcelona Supercomputing Center
Universitat Politècnica de Catalunya. PM - Programming Models
2024
In this era, we are witnessing a huge amount of data growth, and artificial intelligence applications are the only solutions to process this data. These AI applications demand massive computations that a single machine is not capable of. Hence high-performance cluster machines are required. Several Existing HPC clusters are available with x86-64, AMD64, PowerPC, and Arch64 processor architectures; however, a full-stack Open-source software and open hardware clusters are missing. In this work, we have developed an open-hardware RISC-V based HPC cluster using the QEMU simulator. The cluster has a master node and four slave nodes, which are emulated using QEMU. It uses an open-source Linux operating system, distributed and parallel programming and compiler toolchain. The work involved configuring multiple virtual nodes, setting up file systems, establishing networking and installing a distributed compiler toolchain. Several benchmark applications are used to measure the performance of the virtual cluster and compare with that of a physical RISC-V cluster having 4 nodes. The benchmarking was towards execution time and computation cost to evaluate the comparative performance. The findings indicate that the physical cluster performs better than the virtual cluster, with performance difference reaching 50 % under some configurations. Despite these drawbacks, the virtual cluster approach provides a simple and scalable HPC configuration well suited for development and testing, especially when physical resources are limited. This work creates possibilities in utilizing RISC-V for HPC, cloud computing, edge computing, and IoT applications.
The research has received funding from Unal Color of Education Research and Development (UCERD) Private Limited and PakASIC Islamabad.
Peer Reviewed
Postprint (author's final draft)
Conference report
English
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors; HPC; RISC-V; QEMU; ISA
Institute of Electrical and Electronics Engineers (IEEE)
https://ieeexplore.ieee.org/document/10838422
Open Access
E-prints [72263]