Cryogenic CMOS switching power converters

Abstract

Large-scale quantum computers require cryogenic electronic interfaces for qubit control and readout to overcome the wiring bottleneck between room-temperature instrumentation and sub-Kelvin quantum processors. In current systems, powering cryogenic controllers through meter-long low-voltage cables leads to substantial I²R dissipation, increasing the heat load on the dilution refrigerator and limiting scalability. A more scalable approach is to distribute power at higher voltage and lower current, and perform local step-down conversion at the cryogenic stage. This thesis motivates and quantifies the need for cryogenic DC–DC conversion by analyzing power-delivery losses in representative quantum-computing architectures and deriving converter target specifications compatible with the limited cooling budget at 4 K. Building on this system-level analysis, the thesis presents the design and implementation of a fully integrated cryo-CMOS synchronous buck converter intended as a power-management building block for cryogenic controllers. Implemented in 40 nm bulk CMOS, the converter targets a 7 V input, a 1.1 V output, and a 50–300 mA load range. The design employs stacked transistors to satisfy device reliability constraints, a fully integrated on-chip LC output filter, and configurable control supporting both PWM and PFM operation with calibration features to accommodate cryogenic variability. Using EM-extracted passive models with cryogenic parameter adjustments, transistor-level simulations predict up to 63% efficiency at 4 K at 300 mA. These results support high-voltage, low-current power distribution to reduce cable losses and improve system scalability. To the author's best knowledge, no commercially available fully integrated cryogenic regulator provides this combination of input voltage, output voltage, and load capability, positioning the proposed converter as a practical step toward scalable cryogenic power management for future quantum computers.