SORS: Experimentally understanding and efficiently mitigating DRAM read disturbance

Abstract

DRAM chips are increasingly vulnerable to read disturbance phenomena (e.g., RowHammer and RowPress), where repeatedly accessing or keeping open a DRAM row causes bitflips in nearby rows, due to DRAM technology scaling. Even though many prior works develop various RowHammer solutions, these solutions incur nonnegligible and increasingly higher system performance, energy, and hardware area overheads as RowHammer vulnerability worsens. In this talk, we will present recent cutting-edge experimental studies of and solutions to read disturbance. First, we describe variable read disturbance (VRD), a phenomenon that we recently discovered in modern DRAM chips. VRD causes a DRAM row’s read disturbance threshold to change significantly and unpredictably over time, making it difficult to identify the read disturbance threshold and thus develop efficient solutions. Second, we demonstrate that real High Bandwidth Memory (HBM2) chips are largely vulnerable to read disturbance. We also describe the DRAM Bender infrastructure that enabled our discoveries as well as discoveries in other studies (e.g., the RowPress phenomenon). Third, we introduce ABACuS, a low-cost hardware-counter-based RowHammer mitigation technique that performance-, energy-, and area-efficiently scales with worsening RowHammer vulnerability. At very low RowHammer thresholds (where only 125 activations cause a bitflip), ABACuS outperforms and takes up a smaller chip area than the state-of-the-art mitigation techniques. Fourth, we describe Self- Managing DRAM (SMD), a new, low-cost DRAM architecture that enables efficient and autonomous in-DRAM maintenance operations (e.g., periodic and RowHammer-preventive refresh) through a single, simple modification to the DRAM interface. This single modification enables implementing new maintenance mechanisms (or modifying existing ones) with no further changes in the DRAM interface or other system components, thereby enabling innovative ideas in DRAM architecture to rapidly come to fruition. SMD provides substantial performance and energy benefits while also improving system robustness across a variety of workloads.