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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.author | Parcerisa Bundó, Joan Manuel |
dc.contributor.author | González Colás, Antonio María |
dc.date | 2000 |
dc.identifier.citation | Canal, R., Parcerisa, J.M., González, A. Dynamic cluster assignment mechanisms. A: International Symposium on High-Performance Computer Architecture. "Proceedings of the 6th International Symposium on High-Performance Computer Architecture". Toulouse: Institute of Electrical and Electronics Engineers (IEEE), 2000, p. 133-142. |
dc.identifier.citation | 0-7695-0550-3 |
dc.identifier.citation | 10.1109/HPCA.2000.824345 |
dc.identifier.uri | http://hdl.handle.net/2117/100590 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=824345 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Clustered microarchitectures |
dc.subject | Dynamic code partitioning |
dc.subject | Steering logic |
dc.subject | Dynamically scheduled processors |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.title | Dynamic cluster assignment mechanisms |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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