Título:
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A cost-effective clustered architecture
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Autor/a:
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Canal Corretger, Ramon; Parcerisa Bundó, Joan Manuel; González Colás, Antonio María
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Otros autores:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
Abstract:
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In current superscalar processors, all floating-point resources are idle during the execution of integer programs. As previous works show, this problem can be alleviated if the floating-point cluster is extended to execute simple integer instructions. With minor hardware modifications to a conventional superscalar processor, the issue width can potentially be doubled without increasing the hardware complexity. In fact, the result is a clustered architecture with two heterogeneous clusters. We propose to extend this architecture with a dynamic steering logic that sends the instructions to either cluster. The performance of clustered architectures depends on the inter-cluster communication overhead and the workload balance. We present a scheme that uses run-time information to optimise the trade-off between these figures. The evaluation shows that this scheme can achieve an average speed-up of 35% over a conventional 8-way issue (4 int+4 fp) machine and that it outperforms the previously proposed one. |
Abstract:
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Peer Reviewed |
Materia(s):
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-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors -Parallel processing (Electronic computers) -Floating point arithmetic -Parallel architectures -Parallel machines -Performance evaluation -Resource allocation -Processament en paral·lel (Ordinadors) |
Derechos:
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Tipo de documento:
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Artículo - Versión publicada Objeto de conferencia |
Editor:
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Institute of Electrical and Electronics Engineers (IEEE)
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