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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Ratkovic, Ivan |
dc.contributor.author | Palomar Pérez, Óscar |
dc.contributor.author | Stanic, Milan |
dc.contributor.author | Unsal, Osman Sabri |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2018-04-04 |
dc.identifier.citation | Ratkovic, I., Palomar, Ó., Stanic, M., Unsal, O., Cristal, A., Valero, M. Vector processing-aware advanced clock-gating techniques for low-power fused multiply-add. "IEEE transactions on very large scale integration (VLSI) systems", 4 Abril 2018, vol. 26, núm. 4, p. 639-652. |
dc.identifier.citation | 1063-8210 |
dc.identifier.citation | 10.1109/TVLSI.2017.2784807 |
dc.identifier.uri | http://hdl.handle.net/2117/116231 |
dc.language.iso | eng |
dc.relation | https://ieeexplore.ieee.org/document/8252727/ |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2015-65316-P |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/321253 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Microprocessors -- Energy consumption |
dc.subject | Digital arithmetic |
dc.subject | Clock-gating |
dc.subject | Low power |
dc.subject | Vector processors |
dc.subject | Fused multiply-add |
dc.subject | Methodologies |
dc.subject | Microprocessadors -- Consum d'energia |
dc.title | Vector processing-aware advanced clock-gating techniques for low-power fused multiply-add |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/article |
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