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Título: | POSTER: an integrated vector-scalar design on an in-order ARM core |
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Autor/a: | Stanic, Milan; Palomar Pérez, Óscar; Hayes, Timothy; Ratkovic, Ivan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo |
Otros autores: | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
Abstract: | In the low-end mobile processor market, power, energy and area budgets are significantly lower than in other markets (e.g. servers or high-end mobile markets). It has been shown that vector processors are a highly energyefficient way to increase performance; however adding support for them incurs area and power overheads that would not be acceptable for low-end mobile processors. In this work, we propose an integrated vector-scalar design for the ARM architecture that mostly reuses scalar hardware to support the execution of vector instructions. The key element of the design is our proposed block-based model of execution that groups vector computational instructions together to execute them in a coordinated manner. |
Abstract: | Peer Reviewed |
Materia(s): | -Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles -Parallel programming (Computer science) -Architecture -Array processing -Budget control -Commerce -Energy efficiency -Integrated circuit design -Parallel architectures -Parallel processing systems -Vectors -ARM architecture -Energy efficient -Low Power -mobile -Mobile processors -Model of executions -Power overhead -Vector processors -Programació en paral·lel (Informàtica) |
Derechos: | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
Tipo de documento: | Artículo - Versión publicada Objeto de conferencia |
Editor: | Association for Computing Machinery (ACM) |
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