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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Villa, Luis |
dc.contributor.author | Espasa Sans, Roger |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 1997 |
dc.identifier.citation | Villa, L., Espasa, R., Valero, M. Effective usage of vector registers in advanced vector architectures. A: International Conference on Parallel Architectures and Compilation Techniques. "1997 International Conference on Parallel Architectures and Compilation Techniques: San Francisco, California, November 10-14, 1997: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 1997, p. 250-260. |
dc.identifier.citation | 0-8186-8090-3 |
dc.identifier.citation | 10.1109/PACT.1997.644021 |
dc.identifier.uri | http://hdl.handle.net/2117/108431 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/644021/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Performance evaluation |
dc.subject | File organisation |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.title | Effective usage of vector registers in advanced vector architectures |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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