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Effective usage of vector registers in decoupled vector architectures
Villa, Luis; Espasa Sans, Roger; Valero Cortés, Mateo
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
The paper presents a study of the impact of reducing the vector register size in a decoupled vector architecture. In traditional in-order vector architectures long vector registers have typically been the norm. The authors present data which shows that, even for highly vectorizable codes, only a small fraction of all elements of a long vector register are actually used. They also show that reducing the register size in a traditional vector architecture in an attempt to reduce hardware cost and maximize register utilization results in a severe performance degradation. However they combine the decoupling technique with the vector register reduction and show that the resulting architecture tolerates very well the register size cuts. They simulate a selection of Perfect Club and Specfp92 programs using a trace driven approach and compare the execution time in a conventional vector architecture with a decoupled vector architecture using different registers sizes. Halving the register size and using decoupling provides speedups between 1.04-1.49 over a traditional in-order vector machines. Even reducing the register length to 1/4 the original size (and in some cases, to 1/8) the performance of the decoupled machine is better than a conventional vector model. Moreover they observe that the resulting decoupled machine with short registers tolerates very well long memory latencies.
Peer Reviewed
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
Computational complexity
Virtual computer systems
Virtual machines
Vector processor systems
Performance evaluation
Complexitat computacional
Sistemes virtuals (Informàtica)
info:eu-repo/semantics/publishedVersion
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Institute of Electrical and Electronics Engineers (IEEE)
         

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