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dc.contributor | Barcelona Supercomputing Center |
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dc.contributor.author | Trilla, David |
dc.contributor.author | Hernandez, Carles |
dc.contributor.author | Abella, Jaume |
dc.contributor.author | Cazorla, Francisco J. |
dc.date | 2017-07-31 |
dc.identifier.citation | Trilla, D. [et al.]. Modelling bus contention during system early design stages. A: "2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)". IEEE, 2017, p. 1-8. |
dc.identifier.citation | 978-1-5386-3166-9 |
dc.identifier.citation | 10.1109/SIES.2017.7993393 |
dc.identifier.uri | http://hdl.handle.net/2117/107926 |
dc.language.iso | eng |
dc.publisher | IEEE |
dc.relation | http://ieeexplore.ieee.org/document/7993393/ |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2015-65316-P |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2014-60404-JIN |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/RYC-2013-14717 |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria elèctrica |
dc.subject | High performance computing |
dc.subject | Mathematical modelling |
dc.subject | Multicore processing |
dc.subject | Timing |
dc.subject | Program processors |
dc.subject | Load modeling |
dc.subject | Mathematical model |
dc.subject | Schedules |
dc.subject | Analytical models |
dc.subject | Multiprocessing systems |
dc.subject | Real-time systems |
dc.subject | Resource allocation |
dc.subject | System buses |
dc.subject | Supercomputadors |
dc.subject | Matemàtica--Investigació |
dc.title | Modelling bus contention during system early design stages |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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