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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Stanic, Milan |
dc.contributor.author | Palomar Pérez, Óscar |
dc.contributor.author | Hayes, Timothy |
dc.contributor.author | Ratkovic, Ivan |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.author | Unsal, Osman Sabri |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2017-07 |
dc.identifier.citation | Stanic, M., Palomar, Ó., Hayes, T., Ratkovic, I., Cristal, A., Unsal, O., Valero, M. An integrated vector-scalar design on an in-order ARM core. "ACM transactions on architecture and code optimization", Juliol 2017, vol. 14, núm. 2, p. 17:1-17:26. |
dc.identifier.citation | 1544-3566 |
dc.identifier.citation | 10.1145/3075618 |
dc.identifier.uri | http://hdl.handle.net/2117/106671 |
dc.language.iso | eng |
dc.relation | http://dl.acm.org/citation.cfm?id=3075618 |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2015-65316-P |
dc.relation | info:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2015-65316-P |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Integrated circuits -- Design and construction |
dc.subject | Parallel programming (Computer science) |
dc.subject | Computer systems organization |
dc.subject | Single instruction |
dc.subject | Multiple data |
dc.subject | Vector processors |
dc.subject | Low-power |
dc.subject | Energy efficiency |
dc.subject | Mobile processors |
dc.subject | Circuits integrats -- Disseny i construcció |
dc.subject | Programació en paral·lel (Informàtica) |
dc.title | An integrated vector-scalar design on an in-order ARM core |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/article |
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