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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Parcerisa Bundó, Joan Manuel |
dc.contributor.author | González Colás, Antonio María |
dc.date | 2000 |
dc.identifier.citation | Parcerisa, J.M., González, A. Reducing wire delay penalty through value prediction. A: Annual IEEE/ACM International Symposium on Microarchitecture. "33rd Annual ACM/IEEE International Symposium on Microarchitecture: MICRO-33, 2000: 10-13 december 2000: Monterey, California, USA: proceedings". Monterey, California: Institute of Electrical and Electronics Engineers (IEEE), 2000, p. 317-326. |
dc.identifier.citation | 0-7695-0924-X |
dc.identifier.citation | 10.1109/MICRO.2000.898081 |
dc.identifier.uri | http://hdl.handle.net/2117/101126 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/898081/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Computer architecture |
dc.subject | Logic design |
dc.subject | Delays |
dc.subject | Workstation clusters |
dc.subject | Arquitectura d'ordinadors |
dc.subject | Estructura lògica |
dc.title | Reducing wire delay penalty through value prediction |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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