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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Cano Reyes, José |
dc.contributor.author | Kumar, Rakesh |
dc.contributor.author | Brankovic, Aleksandar |
dc.contributor.author | Pavlou, Demos |
dc.contributor.author | Stavrou, Kyriakos |
dc.contributor.author | Gibert Codina, Enric |
dc.contributor.author | Martínez, Alejandro |
dc.contributor.author | González Colás, Antonio María |
dc.date | 2016 |
dc.identifier.citation | Cano, J., Kumar, R., Brankovic, A., Pavlou, D., Stavrou, K., Gibert, E., Martínez, A., González, A. Quantitative characterization of the software layer of a HW/SW co-designed processor. A: IEEE International Symposium on Workload Characterization. "Proceedings of the 2016 IEEE International Symposium on Workload Characterization: September 25-27, 2016 Providence, RI, USA". Providence, Rhode Island: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 138-147. |
dc.identifier.citation | 978-1-5090-3895-4 |
dc.identifier.citation | 10.1109/IISWC.2016.7581274 |
dc.identifier.uri | http://hdl.handle.net/2117/99687 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/7581274/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Microprocessors -- Design and construction |
dc.subject | Hardware-software codesign |
dc.subject | Microprocessor chips |
dc.subject | Optimisation |
dc.subject | Quantitative characterization |
dc.subject | Software layer performance |
dc.subject | HW/SW codesigned processor |
dc.subject | Dynamic binary translation |
dc.subject | Runtime application behavior |
dc.subject | Hybrid architectures |
dc.subject | Translation overheads |
dc.subject | Optimization overheads |
dc.subject | Microarchitectural resources |
dc.subject | Software layer design |
dc.subject | Hardware-software codesigned processor |
dc.subject | Microprocessadors -- Disseny i construcció |
dc.title | Quantitative characterization of the software layer of a HW/SW co-designed processor |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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