Título:
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Quantitative characterization of the software layer of a HW/SW co-designed processor
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Autor/a:
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Cano Reyes, José; Kumar, Rakesh; Brankovic, Aleksandar; Pavlou, Demos; Stavrou, Kyriakos; Gibert Codina, Enric; Martínez, Alejandro; González Colás, Antonio María
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Otros autores:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
Abstract:
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HW/SW co-designed processors currently have a renewed interest due to their capability to boost
performance without running into the power and complexity walls. By employing a software layer that performs dynamic binary translation and applies aggressive optimizations through exploiting the runtime application behavior, these hybrid architectures provide better performance/watt. However, a poorly designed software layer can result in significant translation/optimization overheads that may offset its benefits. This work presents a detailed characterization of the software layer of a HW/SW co-designed processor using a variety of benchmark suites. We observe that the performance of the software layer is very sensitive to the characteristics of the emulated application with a variance
of more than 50%. We also show that the interaction between the software layer and the emulated application, while sharing the microarchitectural resources, can have 0-20% impact on performance. Finally, we identify some key elements which should be further investigated to reduce the observed variations in performance. The paper provides critical insights to improve the software layer design. |
Abstract:
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Peer Reviewed |
Materia(s):
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-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors -Microprocessors -- Design and construction -Hardware-software codesign -Microprocessor chips -Optimisation -Quantitative characterization -Software layer performance -HW/SW codesigned processor -Dynamic binary translation -Runtime application behavior -Hybrid architectures -Translation overheads -Optimization overheads -Microarchitectural resources -Software layer design -Hardware-software codesigned processor -Microprocessadors -- Disseny i construcció |
Derechos:
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Tipo de documento:
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Artículo - Versión presentada Objeto de conferencia |
Editor:
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Institute of Electrical and Electronics Engineers (IEEE)
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