Para acceder a los documentos con el texto completo, por favor, siga el siguiente enlace: http://hdl.handle.net/2117/166688
dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
---|---|
dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Bosch, Jaume |
dc.contributor.author | Tan, Xubin |
dc.contributor.author | Filgueras Izquierdo, Antonio |
dc.contributor.author | Vidal, Miquel |
dc.contributor.author | Mateu, Marc |
dc.contributor.author | Jiménez-González, Daniel |
dc.contributor.author | Álvarez, Carlos |
dc.contributor.author | Martorell Bofill, Xavier |
dc.contributor.author | Ayguadé Parra, Eduard |
dc.contributor.author | Labarta Mancho, Jesús José |
dc.date | 2019 |
dc.identifier.citation | Bosch, J. [et al.]. Application Acceleration on FPGAs with OmpSs@FPGA. A: International Conference on Field-Programmable Technology. "2018 International Conference on Field-Programmable Technology (FPT 2018): Naha, Okinawa, Japan: 10-14 December 2018". Institute of Electrical and Electronics Engineers (IEEE), 2019, p. 73-80. |
dc.identifier.citation | 9781728102153 |
dc.identifier.citation | 10.1109/FPT.2018.00021 |
dc.identifier.uri | http://hdl.handle.net/2117/166688 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | https://ieeexplore.ieee.org/document/8742333 |
dc.relation | info:eu-repo/grantAgreement/EC/H2020/754337/EU/Co-designed Innovation and System for Resilient Exascale Computing in Europe: From Applications to Silicon/EuroEXA |
dc.relation | info:eu-repo/grantAgreement/EC/H2020/687698/EU/High Performance and Embedded Architecture and Compilation/HiPEAC |
dc.relation | info:eu-repo/grantAgreement/ES/1PE/TIN2015-65316-P |
dc.relation | info:eu-repo/grantAgreement/AGAUR/PRI2010-2013/2014 SGR 1051 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles |
dc.subject | Field programmable gate arrays |
dc.subject | Task analysis |
dc.subject | Field programmable gate arrays |
dc.subject | Runtime |
dc.subject | Switched mode power supplies |
dc.subject | Tools |
dc.subject | IP networks |
dc.subject | Kernel |
dc.subject | Matrius de portes programables per l'usuari |
dc.title | Application Acceleration on FPGAs with OmpSs@FPGA |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
dc.description.abstract | |
dc.description.abstract | |
dc.description.abstract |