dc.contributor |
Barcelona Supercomputing Center |
dc.contributor.author |
Milutinovic, Suzana |
dc.contributor.author |
Mezzetti, Enrico |
dc.contributor.author |
Abella, Jaume |
dc.contributor.author |
Cazorla, Francisco J. |
dc.date |
2019-06-01 |
dc.identifier.citation |
Milutinovic, S. [et al.]. Increasing the Reliability of Software Timing Analysis for Cache-Based Processors. "IEEE Transactions on Computers", 1 Juny 2019, vol. 68, núm. 6, p. 836-851. |
dc.identifier.citation |
0018-9340 |
dc.identifier.citation |
10.1109/TC.2018.2890626 |
dc.identifier.uri |
http://hdl.handle.net/2117/132948 |
dc.language.iso |
eng |
dc.publisher |
IEEE |
dc.relation |
https://ieeexplore.ieee.org/abstract/document/8603793 |
dc.relation |
info:eu-repo/grantAgreement/ES/PE2013-2016/TIN2015-65316-P |
dc.relation |
info:eu-repo/grantAgreement/ES/PE2013-2016/BES-2016-077561 |
dc.relation |
info:eu-repo/grantAgreement/ES/PE2013-2016/RYC-2013-14717 |
dc.relation |
info:eu-repo/grantAgreement/ES/PE2013-2016/IJCI-2016-27396 |
dc.rights |
info:eu-repo/semantics/openAccess |
dc.subject |
Àrees temàtiques de la UPC::Informàtica |
dc.subject |
Computer software |
dc.subject |
Computers |
dc.subject |
Timing |
dc.subject |
Hardware |
dc.subject |
Safety |
dc.subject |
Software |
dc.subject |
Automotive engineering |
dc.subject |
Probabilistic logic |
dc.subject |
Standards |
dc.subject |
Programari |
dc.subject |
Ordinadors |
dc.title |
Increasing the Reliability of Software Timing Analysis for Cache-Based Processors |
dc.type |
info:eu-repo/semantics/submittedVersion |
dc.type |
info:eu-repo/semantics/article |
dc.description.abstract |
Real-time systems are witnessing a significant increase in critical software's size, complexity, and performance needs, which can only be satisfied with high-performance hardware features. Cache memories, pervasively used to improve average performance, complicate Worst-Case Execution Time analysis: cache placement (i.e., how software objects are mapped to cache) during the testing phase does not only critically affect the observed performance, but also proves to be arduous to control and preserve up to operation. The probabilistic variant of Measurement-Based Timing Analysis (MBPTA) responds to this challenge by deploying time-randomized caches that naturally explore a different random cache placement in each run, relieving the user from producing tests that intercept relevant Cache Conflict Placements (CCP). Yet, to meet an adequate probabilistic CCP coverage, the user is required to collect a minimum number of measurements. We present two mechanisms, CCP-RM and CCP-HRP, to identify CCP with relevant probability of occurrence and large impact on execution-time, for the random modulo (RM) and hash-based random placement (HRP) policies. CCP-RM and CCP-HRP enable a reliable application of MBPTA by computing the number of runs $R^{\prime }$R' necessary to meet the desired CCP coverage. We exhaustively evaluate CCP-RM and CCP-HRP, showing their effectiveness on well-known benchmarks and a railway case study, on top of an accurate simulator and a concrete RTL implementation. |
dc.description.abstract |
This work has received funding from the Spanish Ministry of Science and Innovation under grant TIN2015-65316-P and the HiPEAC Network of Excellence. The Ministry of Economy and Competitiveness partially supported Suzana Milutinovic under FPI grant (BES-2016-077561), Jaume Abella under
Ramon y Cajal postdoctoral fellowship (RYC-2013-14717) and Enrico Mezzetti under Juan de la Cierva-Incorporación postdoctoral fellowship (IJCI-2016-27396). |
dc.description.abstract |
Peer Reviewed |