Verification of timed circuits with symbolic delays

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Título:	Verification of timed circuits with symbolic delays
Autor/a:	Clarisó Viladrosa, Robert; Cortadella, Jordi
Otros autores:	Universitat Politècnica de Catalunya. Departament de Ciències de la Computació; Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
Abstract:	Verifying timed circuits is a complex problem even when the delays of the system are fixed. This paper deals with a more challenging problem, the formal verification of timed circuits with unspecified delays represented as symbols. The approach discovers a set of sufficient linear constraints on the symbols that guarantee the correctness of the circuit. Experimental results from the area of asynchronous circuits show the applicability of the approach.
Abstract:	Peer Reviewed
Materia(s):	-Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats -Integrated circuits -- Verification -Timing -Delay systems -Flip-flops -Clocks -Formal verification -Asynchronous circuits -Wires -Information analysis -Feedback -Automatic testing -Circuits integrats -- Verificació
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Tipo de documento:	Artículo - Versión publicada Objeto de conferencia
Editor:	Institute of Electrical and Electronics Engineers (IEEE)
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Clarisó Viladrosa, Robert; Cortadella, Jordi

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