Automatic microarchitectural pipelining

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dc.contributor	Universitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.contributor	Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.contributor.author	Galcerán Oms, Marc
dc.contributor.author	Cortadella, Jordi
dc.contributor.author	Bufistov, Dmitry
dc.contributor.author	Kishinevsky, Michael
dc.date	2010
dc.identifier.citation	Galceran, M. [et al.]. Automatic microarchitectural pipelining. A: Design, Automation and Test in Europe Conference and Exhibition. "Design, Automation & Test in Europe: Dresden, Germany, March 8-12, 2010: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2010, p. 961-964.
dc.identifier.citation	978-3-9810801-6-2
dc.identifier.citation	10.1109/DATE.2010.5456910
dc.identifier.uri	http://hdl.handle.net/2117/132753
dc.language.iso	eng
dc.publisher	Institute of Electrical and Electronics Engineers (IEEE)
dc.relation	https://ieeexplore.ieee.org/document/5456910
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject	Computers, Pipeline
dc.subject	Microprocessors -- Design and construction
dc.subject	Microarchitecture
dc.subject	Pipeline processing
dc.subject	Counting circuits
dc.subject	Delay
dc.subject	Space exploration
dc.subject	Wires
dc.subject	Design automation
dc.subject	Design optimization
dc.subject	Clocks
dc.subject	Protocols
dc.subject	Microprocessadors -- Disseny i construcció
dc.title	Automatic microarchitectural pipelining
dc.type	info:eu-repo/semantics/publishedVersion
dc.type	info:eu-repo/semantics/conferenceObject
dc.description.abstract	This paper presents a method for automatic microarchitectural pipelining of systems with loops. The original specification is pipelined by performing provably-correct transformations including conversion to a synchronous elastic form, early evaluation, inserting empty buffers, anti-tokens, and retiming. The design exploration is done by solving an optimization problem followed by simulation of solutions. The method is explained on a DLX microprocessor example. The impact of different microarchitectural parameters on the performance is analyzed.
dc.description.abstract	Peer Reviewed

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