To access the full text documents, please follow this link: http://hdl.handle.net/2117/129522
dc.contributor | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació |
---|---|
dc.contributor | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
dc.contributor.author | Lang, Tomás |
dc.contributor.author | Cortadella, Jordi |
dc.contributor.author | Musoll Cinca, Enric |
dc.date | 1997-06 |
dc.identifier.citation | Lang, T.; Cortadella, J.; Musoll, E. Individual flip-flops with gated clocks for low power datapaths. "IEEE transactions on circuits and systems II: analog and digital signal processing", Juny 1997, vol. 44, núm. 6, p. 507-516. |
dc.identifier.citation | 1057-7130 |
dc.identifier.citation | 10.1109/82.592586 |
dc.identifier.uri | http://hdl.handle.net/2117/129522 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | https://ieeexplore.ieee.org/document/592586 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject | Logic circuits |
dc.subject | Microprocessors -- Energy consumption |
dc.subject | Flip-flops |
dc.subject | Clocks |
dc.subject | Energy consumption |
dc.subject | CMOS technology |
dc.subject | Digital systems |
dc.subject | Batteries |
dc.subject | Wireless communication |
dc.subject | Power system modeling |
dc.subject | Circuit simulation |
dc.subject | Registers |
dc.subject | Circuits lògics |
dc.subject | Microprocessadors -- Consum d'energia |
dc.title | Individual flip-flops with gated clocks for low power datapaths |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/article |
dc.description.abstract | |
dc.description.abstract |