An asynchronous architecture model for behavioral synthesis

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Title:	An asynchronous architecture model for behavioral synthesis
Author:	Cortadella, Jordi; Badia Sala, Rosa Maria
Other authors:	Universitat Politècnica de Catalunya. Departament de Ciències de la Computació; Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
Abstract:	An asynchronous architecture model for behavioral synthesis is presented. The basis of the model lies in a distributed control structure consisting of multiple communicating processes. Data processing is performed by self-timed modules. Signal transition graphs (STGs) are used to specify the behavior of the control processes. By using existing synthesis procedures for STGs, circuits based on the presented architecture model are proved to be realizable and hazard-free.
Abstract:	Peer Reviewed
Subject(s):	-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors -Logic design -Asynchronous sequential logic -Computer architecture -Directed graphs -Distributed control -Logic CAD -Estructura lògica
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Document type:	Article - Published version Conference Object
Published by:	Institute of Electrical and Electronics Engineers (IEEE)
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