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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.contributor.author | Aragón, Juan Luis |
dc.contributor.author | González González, José |
dc.contributor.author | González Colás, Antonio María |
dc.date | 2003 |
dc.identifier.citation | Aragón, J., González, J., González, A. Power-aware control speculation through selective throttling. A: International Symposium on High-Performance Computer Architecture. "The Ninth International Symposium on High-Performance Computer Architecture, HPCA–9 2003: February 8-12, 2003, Anaheim, California: proceedings". Anaheim, California: Institute of Electrical and Electronics Engineers (IEEE), 2003, p. 103-112. |
dc.identifier.citation | 0-7695-1871-0 |
dc.identifier.citation | 10.1109/HPCA.2003.1183528 |
dc.identifier.uri | http://hdl.handle.net/2117/100847 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/1183528/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Parallel processing (Electronic computers) |
dc.subject | Microprocessors -- Energy consumption |
dc.subject | Delays |
dc.subject | Parallel architectures |
dc.subject | Performance evaluation |
dc.subject | Pipeline processing |
dc.subject | Power consumption |
dc.subject | Power control |
dc.subject | Processament en paral·lel (Ordinadors) |
dc.subject | Microprocessadors -- Consum d'energia |
dc.title | Power-aware control speculation through selective throttling |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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